In a development of a computer system, a logic circuit is generally verified by logic simulation before a computer system is actually fabricated.
In order to develop a computer system of less failure, it is important to verify a logic circuit having the same configuration as an actual computer system to be fabricated. For the above, it is desired to create a verification model having the same configuration as the maximum configuration of the computer system can have.
Hereinafter, description will now be made, assuming that a verification model having the entire configuration of a computer system is formed on a large-scale simulator.
FIG. 13 is a block diagram illustrating an example of the configuration of a computer system on a simulator. As illustrated in FIG. 13, a computer system 100 (hereinafter simply called “system”) includes CPUs (Central Processing Units) 200-1 and 200-2, controllers 300-1 through 300-4, memories 400-1 through 400-4, IO (Input Output) controller 500, and IO cards 600-1 and 600-2.
Hereinafter, reference numbers 200-1 and 200-2 are used for CPUs when one of the CPUs is specified, and an arbitrary CPU is represented by reference number 200; reference numbers 300-1 through 300-4 are used for controllers when one of the controllers is specified, and an arbitrary controller is represented by reference number 300; reference numbers 400-1 and 400-4 are used for memories when one of the memories is specified, and an arbitrary memory is represented by reference number 400; and reference numbers 600-1 and 600-2 are used for IO cards when one of the IO cards is specified, and an arbitrary IO card is represented by reference number 600.
The CPUs 200-1 and 200-2 each read a program stored in the respective memories or the like and carry out predetermined processing. Here, the CPUs 200-1 and 200-2 reads a logic verifying program from the respective memory 400 and carries out logical verification on the system 100. As the above, in a computer system, the CPU 200 processes instructions followed by reading and writing data into and from a memory 400 through fetching instructions, fetching data, and storing data.
The CPU 200-1 includes a calculating unit 210-1 and a selecting unit 250-1; and the CPU 200-2 includes a calculating unit 210-2 and a selecting unit 250-2.
The calculating units 210-1 and 210-2 carry out predetermined calculations exemplified by issuing instructions for accesses to the memories 400 and the IO cards 600. When the CPU 200-1 and 200-2 access the memories 400 and the IO cards 600, the selecting units 250-1 and 250-2 select routes through which accesses are output.
The controllers 300-1 through 300-4 each controls accesses from the CPUs 200 and the IO controllers 500 to the controllers 400. The controller 300 is exemplified by a system controller.
Here, in the system 100 illustrated in FIG. 13, the selecting units 250-1 is communicably connected to the controllers 300-1 through 300-4, and similarly the selecting units 250-2 is communicably connected to the controllers 300-1 through 300-4.
The controllers 300-1 through 300-4 are communicably connected to each other.
The memories 400-1 through 400-4 each includes storing region having an address uniquely defined in the system 100. When the CPU 200 is executing a program, the CPU 200 reads the program from the storing region and stores and extends data and programs on the storing region. An example of the memory 400 is a RAM (Random Access Memory).
The IO controller 500 controls access from the CPU 200 to the IO cards 600, and also controls access from the IO card 600 to the memories 400. The IO controller 500 includes an arbitration unit 510.
The IO controller 500 is connected to the controller 300-1 and accesses the memory 400-1, the memory 400-2 connected to the controller 300-2, the memory 400-3 connected to the controller 300-3, and the memory 400-4 connected to the controller 300-4 through the controller 300-1.
The arbitration unit 510 arbitrates accesses from a number of IO cards 600 and distributes access from the CPUs 200 or the like to either IO card 600-1 and 600-2.
The IO cards 600-1 and 600-2 each controls connection between the system 100 and an external device connected via an auxiliary unit or a LAN.
As the illustrated in example FIG. 13, the system 100 includes four controllers 300-1 through 300-4 connected to the memories 400-1 through 400-4, respectively.
Here, addresses of the memories 400-1 through 400-4 are interleaving controlled by the four controllers 300-1 through 300-4 with the intention of speeding up the accesses to the memories 400.
An address of an entity other than the memories 400 such as the IO controllers 500 is not interleaving controlled. Accordingly, an access from the CPU 200 to the IO controllers 500 is made from the selecting unit 250 through the controller 300-1.
The controller 300 carries out interleaving controlling by sequentially selecting four controllers 300-1 through 300-4 in units of a predetermined address width of the memories 400, e.g. in units of 64 bytes. Thereby, when the CPU 200 makes accesses to continuous addresses of the memories 400, the controllers 300-1 through 300-4 and the memories 400-1 through 400-4 connected to the respective controllers 300 are evenly used.
Namely, a number of controllers 300 and a number of memories 400 installed in the computer system are uniquely selected by the addresses of the memories 400.
FIG. 14 is a flow diagram illustrating a succession of procedural steps of general address processing performed by a CPU 200.
For example, as illustrated in FIG. 14, when the calculating unit 210 in the CPU 200 issues an access request to the memory 400, the calculating unit 210 generates an address of an access destination (step S101).
Next, selecting unit 250 judges whether the address of the access destination is an address of a memory 400 or an address of the IO controller 500. Then, the selecting unit 250 selects a controller through which the is sued access request is output. Namely, the selecting unit 250 selects one of the four controllers 300-1 through 300-4 connected to the CPU 200 through which the issued access request is output (step S102).
Thereby, if the access destination is an address of the memory 400-1, the CPU 200-1 makes an access through the controller 300-1 to the memory 400-1; if the access destination is an address of the memory 400-2, the CPU 200-1 makes an access through the controller 300-2 to the memory 400-2; if the access destination is an address of the memory 400-3, the CPU 200-1 makes an access through the controller 300-3 to the memory 400-3; and if the access destination is an address of the memory 400-4, the CPU 200-1 makes an access through the controller 300-4 to the memory 400-4. In contrast, if the access destination is an address of the IO controller 500, the CPU 200 makes an access through the controller 300-1 to the IO controller 500.
FIG. 15 is a flow diagram illustrating a succession of procedural steps of general address processing of the IO controller 500.
For example, as illustrated in FIG. 15, an access request is input from the IO card 600 into the IO controller 500. In other words, the IO card 600 generates an address that indicates an access destination, and outputs the generated address to the IO controller 500 (step S111).
Next, the arbitration unit 510 of the IO controller 500 arbitrates an access from the IO card 600 on the basis of the address of an access destination input from the IO card 600. Specifically, the IO card 600 from which an access request is to be issued is selected from the IO cards 600-1 and 600-2 (step S112).
Then, if the address of the access destination is an address of memory 400, the IO controller 500 makes an access to the address of the access destination through the controller 300-1 connected to the IO controller 500 (step S113).
Thereby, if the address of an access destination is an address of the memory 400-1, the IO controller 500 makes an access through the controller 300-1 to the memory 400-1; if the address of an access destination is an address of the memory 400-2, the IO controller 500 makes an access through the controllers 300-1 and 300-2 to the memory 400-2; if the address of an access destination is an address of the memory 400-3, the IO controller 500 makes an access through the controllers 300-1 and 300-3 to the memory 400-3; and if the address of an access destination is an address of the memory 400-4, the IO controller 500 makes an access through the controllers 300-1 and 300-4 to the memory 400-4.
Here, the address of the memory 400 uses a continuous region of several Kilobytes through several Megabytes in the instruction region and the data region. Furthermore, interleaving by the controller 300 spreads regions storing instructions and data that the memories 400 processes to all the controllers 300 in the computer system.
Accordingly, an access request from the CPU 200 or the IO controllers 500 to a memory 400 are output to all the controllers 300-1 through 300-4 uniquely selected by the addresses of the memories 400.
[Patent Document] Japanese Laid-Open Patent Publication No. HEI 01-243136
In recent years, since the degree of integration of a semiconductor increases due to development of finer processing, it is difficult to verify, decreasing the number of the overlooked verification models, whether a computer system correctly operates through logic simulation using verification models.
As illustrated above with reference to FIGS. 13 through 15, for development of a computer system of less fails, it is important to verify a logical circuit through logic simulation on the same configuration as the computer system to be developed. This desires a verification model having the maximum configuration of the computer system.
However, in accordance with the capacity increase of the logical circuit of a computer system resulting from improvement of finer semiconductors, the verification model of a large-scale computer system uses a simulator large in capacity and high in cost.
In the meantime, since a simulator can accommodate a limited capacity of a logic circuit, some verification models of a large-scale computer system exceed the capacity of a simulator so that verification may not be accomplished.
For example, a storing unit such as memory usually uses a continuous region of several Kilobyte through several Megabyte to store a test program and data for logic verification.
On the other hand, a computer system that interleaving controls the memories uniformly uses the respective controllers and the memories by sequentially selecting four controllers in units of a predetermined address width, for example, in units of 64 byte as described above with reference to FIG. 13.
As the above, in a computer system that interleaving controls the memories, a region of a memory is allocated to the respective controller in units of a predetermined address width.
In such a computer system, even if a verification model does not accommodate one of the controllers and one of the memories, the logic verification carries out interleaving control as the above. Accordingly, the region of a memory seen from a test program for logic verification does not have a region of a predetermined address width that is periodically assigned to the memory accommodated in the verification model, which makes the logical verification difficult.
As the above, it is preferable to generate verification model which covers all the combinations of controllers that perform interleaving control in order to ensure a continuous region of the memory.
However, in logic verification of a computer system, insufficient capacity of the simulation to accommodate all the combinations of controllers may unsuccessfully configure the verification model.
Conventionally, in the cases where it is difficult to create a verification model of a large-capacity computer system, the verification has been carried out by one of the following schemes (i) through (iii).
(i) preparing a larger-capacity simulator and carrying out verification;
(ii) reducing elements such as a CPU except for controllers, and creating a less-capacity model to verification; and
(iii) creating an artificial circuit of a controller or the like to reduce the capacity, substituting the artificial circuit for the controller, and carrying out the verification.
However, in the above scheme (i), a larger-capacity simulator is determined, requiring an expensive simulator, which therefore raises the costs. Moreover, there may not be a simulator having a sufficient capacity to verify the configuration of a large-scale computer system.
In such a case, a possible solution is to create a verification model having the maximum configuration that the capacity of the simulator allows. However, if memories are interleaving controlled, a verification model preferably includes a number of controllers. Accordingly, in creating a verification model, since the number of controllers is not less than the minimum unit that constitutes the interleaving (system), so that a verification model may not be configured.
In the scheme (ii), when reducing elements such as a CPU except for controllers and creating a less-capacity model to verification, the omitted elements by the reduction are not verified, which makes the verification difficult to reduce the verification models that are overlooked.
In addition, a verification model is different in configuration from that of the computer system, which results in modifying the test program and thereby increases a number of steps in development.
In the scheme (iii), when creating an artificial circuit of a controller or the like to reduce the capacity and substituting the artificial circuit for the controller, an extra artificial circuit is created, which increases a number of steps in development.
Furthermore, the following problems arise.
A general logic verification scheme on a computer system concentrates access to a particular memory or diffusing accesses with the intention of improving verification coverage. In order to carryout this scheme, a large number of test programs are created for each address for which access is desired to be concentrated or diffused.
However, creation of such a large number of test programs increases the number of steps in development.